1. Field of the Invention
The present invention relates generally to a circuit and method for controlling inversion of a Delay Locked Loop (DLL), and a synchronous semiconductor memory device incorporating such a DLL.
A claim of priority is made to Korean Patent Application No. 2003-96385 filed on Dec. 24, 2003, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
In many applications involving the transmission of various signals, it is critical to accurately reproduce signal timing characteristics upon reception of, or prior to transmission of the signals. That is, the signals must typically be synchronized in their transmission and reception to a standard timing signal (e.g., a clock). A Phase Locked Loop (PLL) or a DLL is commonly used to synchronize the timing characteristics of one or more signals.
The conventional PLL generates a voltage control signal corresponding to a phase difference between an external clock signal and a reproduction clock signal. The phase of the reproduction clock signal is adjusted in relation to the voltage control signal to follow the phase of the external clock signal by means of varying the frequency of the reproduction clock signal.
The conventional DLL similarly generates a voltage control signal corresponding to a phase difference between the external clock signal and the reproduction clock signal, but adjusts a delay period for the reproduction clock signal in response to the voltage control signal to thereby control the phase of the reproduction clock signal such that it follows the phase of the external clock signal.
A DLL is commonly used in digital signal processing systems and synchronous memory devices, such as Synchronous Dynamic Random Access Memory (SDRAM). Common DLL configurations use an inversion scheme that provides a fast locking of signals at the beginning of a phase locking operation.
Referring to FIG. 1, a typical inversion scheme implemented in a DLL circuit compares the phase of a received external clock signal (EXCLK) with the phase of a reproduction clock signal (RCLK) in order to generate (i.e., “output”) the reproduction clock signal RCLK without inversion when the phase difference, τ 1, between the clock signals EXCLK and RCLK is greater than one half of a cycle, (i.e., T/2(τ 1<T/2)). (See, timing relationship (iii) in FIG. 1). In contrast, an inverted reproduction clock signal (RCLKB) is output when the phase difference, τ 2, is less than one half of a cycle (i.e., T/2 (τ 2<T/2)). (See, timing relationship (ii) in FIG. 1). Within the foregoing timing relationships, the “following time”(i.e., a delay time) required to lock the rising edge of RCLK to the rising edge of EXCLK can be reduced to no more than half a clock cycle.
However, this is not the case where the duty cycle ratio of RCLK falls below 50%. (See, timing relationship (i) in FIG. 1). In such cases, the reproduction clock signal ERCLK must be delayed by more than half a cycle when inversion is performed because otherwise the phase difference during the next cycle would be mistakenly seen as being less than a half cycle despite the phase difference actually being more than a half cycle.
Thus, DLLs using the inversion scheme experience a problem in that the initial locking time is additionally delayed by as much as the change of the duty cycle ratio for the reproduction clock signal RCLK. Operating speed suffers accordingly when one cycle of the clock signal is larger than a predetermined maximum delay period, and phase unlocking may occur because the locking delay adjustment cannot be performed for such delay periods.